FIG. 16 shows an example of a structure of a disk array device according to related art. A disk control device of the disk array device comprises host interfaces (Host I/F) 501 and 502 to be connected to a host computer which accesses to the disk array device, a plurality of disk interfaces (Disk I/F) 503 and 504 to be connected to a disk enclosure, a plurality of processors 201 through 204 which execute processing of writing and reading data to/from the host computer and the disk enclosure, and switches 400 and 401 which connect the host interface and the disk interface, and a plurality of processors. In the figure, the interface indicated as xxI/F functions as either a host interface or a disk interface.
The host interfaces 501 and 502 and the disk interfaces 503 and 504 each have a processor 600 which, upon receiving an access request from the host computer, selects a plurality of processors which execute data read and write processing and communicate with the selected processors, and they are each structured by the same unit as that of the processor 600. The processors 201 through 204 have caches 301 through 304.
In the conventional disk array device shown in FIG. 16, assignment of the processors 201 through 204 to the host interfaces 501 and 502 and the disk interfaces 503 and 504 is fixed to fix an internal flow of data.
Related art of thus structured disk array device is recited, for example, in Patent Literature 1 and Patent Literature 2.    Patent Literature 1: Japanese Patent Laying-Open No. 2006-107019.    Patent Literature 2: Japanese Patent Laying-Open No. 2006-252019.
The structure of the above-described disk array device according to the related art has the following problems.
First problem is that because assignment of processors to a host interface and a disk interface is fixed, the degree of freedom of unit expansion is low, so that an optimum structure is hard to be adopted according to costs and necessary performance of a disk array device.
Second problem is that because assignment of processors to a host interface and a disk interface is fixed, under some conditions of use of a disk array device, it is impossible to distribute processor loads, so that a heavy load processor is liable to bottleneck performance of the entire device.
Third problem is that because processors on a host interface and a disk interface select a processor which will execute data read and write processing and communicate with the selected processor, this is one of factors in increasing a load on a processor which executes data read and write processing.
Fourth problem is that because a host interface and a disk interface comprise a processor which selects a plurality of processors that execute data read and write processing and communicates with the selected processors, a unit forming the host interface and the disk interface is increased in size to limit the number of interfaces mounted.